Self-error injection technique for point-to-point interconnect to increase test coverage

ABSTRACT

Various aspects describe an on-chip, hardware error-generator component. In some cases, the hardware error-generator component connects to a data path between two components contained within a same chip. Upon receiving an error simulation input, the hardware error-generator component modifies data being transmitted on the data path by inserting a data pattern that simulates an error condition. Alternately or additionally, the hardware error-generator randomly alters one or more of the transmitted data bits.

RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent ApplicationNo. 62/222,726, filed Sep. 23, 2015, the disclosure of which isincorporated by reference herein in its entirety.

BACKGROUND

Field of the Disclosure

This disclosure relates generally to error-injection control and, morespecifically, to on-chip error-generator components.

Description of Related Art

Computing devices today conventionally include multiple components thatare interconnected with one another through data lines. Each componentperforms a respective functionality and interconnects with one anotherto request or share results. Thus, data lines are used by the componentsto communicate data or information back and forth to achieve an overallgoal. Ideally, data lines successfully transmit and receive data withouterror. However, in a real-world implementation, physical propertiesintroduce error into the data lines, corrupting the data beingtransferred. Since real-world effects cannot be eradicated completely, aviable alternative ensures that errors are handled properly. Sinceerrors can manifest in a variety of ways, it can be challenging,especially in multiple-component devices, to ensure that all possibleerrors are handled properly. This is due to the limited number ofinterfaces available to test a multi-component device.

SUMMARY

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter.

One aspect of the disclosure describes a device for testing errorhandling, the device comprising: at least one error insertion circuit;an on-chip hardware error-generator component coupled, via the at leastone error insertion circuit, to at least one data line between twosub-components in the device, the on-chip hardware error-generatorcomponent configured to: receive an error simulation input; determine adata error pattern based, at least in part, on the error simulationinput; and insert the data error pattern, via the at least one errorinsertion circuit, on the at least one data line effective to generatean error condition.

One aspect of the disclosure describes a method for testing errorhandling, the method comprising: receiving, using a hardwareerror-generator component, an error simulation input; determining, usingthe hardware error-generator component, a data error pattern to inserton at least one digital data line coupled to the hardwareerror-generator component; and inserting, using the hardwareerror-generator component, the data error pattern on the at least onedigital data line effective to generate an error condition.

One aspect of the disclosure describes an apparatus for testing errorhandling, the apparatus comprising: an on-chip sub-component of theapparatus operatively coupled to a data path; and an on-chip hardwareerror-generator component operatively coupled to the data path andcomprising: means for receiving error simulation input; means fordetermining at least one data error pattern based, at least in part, onthe error simulation input; and means for inserting the at least onedata error pattern on the data path effective to generate an errorcondition into the on-chip sub-component of the apparatus.

One aspect of the disclosure describes one or more computer-readablememory devices comprising processor-executable instructions which,responsive to execution by at least one processor, perform operations tosimulate on-chip error generation using one or more components of anemulated integrated circuit (IC), the operations comprising: receivingan error simulation input at an on-chip hardware error-generatorcomponent of the emulated IC; determining a data error pattern based, atleast in part, on the error simulation input; and inserting the dataerror pattern on at least one data line coupled to the on-chip hardwareerror-generator effective to generate an error condition into asub-component of the emulated IC that is coupled to the at least onedata line.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description references the accompanying figures. In thefigures, the left-most digit(s) of a reference number identifies thefigure in which the reference number first appears. The use of the samereference numbers in different instances in the description and thefigures may indicate similar or identical items.

FIG. 1 is an illustration of an example environment in which hardware,error-generator components can be employed.

FIG. 2 is an illustration of example ideal and distorted data signals.

FIGS. 3a and 3b are illustrations of system-on-chip circuits in whichhardware, error-generator components are employed to test error handlingfunctionality.

FIG. 4 is a flow diagram that describes a method that employs hardwareerror-generator components.

FIG. 5 is an example system which illustrates on-chip, sub-componentinterconnections that employ hardware, error-generator components fortesting purposes.

DETAILED DESCRIPTION Overview

To ensure robust products, error handling functionality can be added toaccount for possible error conditions, such as errors caused by datacorruption or loss of data. Consider an example where interconnectedcomponents in a wireless modem share data with one another over digitaldata lines. In one possible error scenario, a receiving componentexpects to receive a first set of data, but instead receives a secondset of data that includes corrupted data. Instead of hanging or haltingthe actions of the receiving component due to corrupted data (or theoverall functionality of the wireless modem itself), error handlingfunctionality can be used to identify when corrupted data has beenreceived. Upon identifying corrupted data, error handling functionalitygenerates or executes a response to handle the error, such as byreturning information to the sending component indicating that corrupteddata has been received, using bit recovery techniques as an attempt torecover the corrupted data, and so forth. By including error handlingfunctionality, a component will still yield reliable results, even whenpresented with corrupted data, thus preventing the overall functionalityfrom hanging. In turn, this yields a more robust product. However, eventhe error handling can be prone to errors. Thus, a product is only asrobust as its associated error handling, and it is desirable to verifythat the error handling works as expected.

Testing a complex product for errors, and proper error handling, posescertain challenges. Consider the example of an integrated circuit (IC)that includes multiple sub-components interconnected through data lines.ICs have finite inputs and outputs used to access the IC which, in turn,can be used to test overall functionality of an IC. “Black-box” testingof an IC inputs known data through the corresponding input, and monitorsthe outputs for expected results. Here, the inner workings of the IC arenot exposed. If the IC exhibits faulty behavior by returning unexpectedresults, it can be problematic identifying where in the interconnectedsub-components problems originate. Further, the nature of “black-box”testing can make it difficult to guarantee that all error cases havebeen exercised or tested, particularly those referred to as “cornercases”. Corner cases can vary from system to system but conventionallyinclude those cases that occur infrequently.

To ensure a wide variety of test coverage scenarios, including so-called“corner cases”, on-chip, hardware error-generator components areutilized to accurately control error injection and the timing thereofThe hardware error-generator components provide for flexibility andexpandability to allow for testing to be performed in the pre-siliconplatform and post-silicon platform, as well as customer sample systems.In at least one aspect, the hardware error-generator component is acomponent on an IC, such as a silicon chip. The hardware error-generatorcomponent can connect to a data path between two sub-componentscontained within the chip and, upon receiving an error simulation input,modify data being transmitted on the data path. In some cases, the datais modified randomly, while in other cases, a known data pattern isselected based upon the error simulation input. The data pattern is theninserted on the data path effective to generate an error condition.Another error simulation input can be used to return the data path backto its original transmission state (e.g., unaltered).

In the following discussion, an example environment is first describedthat may employ the techniques described herein. Example procedures arethen described which may be performed in the example environment as wellas other environments. Consequently, performance of the exampleprocedures is not limited to the example environment and the exampleenvironment is not limited to performance of the example procedures.

Example Environment

FIG. 1 illustrates example environment 100 comprising user device 102.Here, user device 102 is shown as a cellular mobile device, but anysuitable type of computing device, such as a tablet, laptop computer, aset-top box, satellite receiver, cable television receiver, Wi-Fi accesspoint, desktop computer, gaming device, display device, or the like canbe used. In this example, user device 102 includes wirelesscommunication capabilities, and is configured to communicate with any orall of cell towers 104-1 through 104-n, where “n” represents anarbitrary number. These cell towers work in conjunction to communicatewith user device 102 and allow user device 102 to move from location tolocation without losing a communication link. Here, user device 102includes modem 106 to perform at least part of these communications.

Modem 106 transmits and receives wireless signals and/or data. In someaspects, modem 106 is a circuit board that electrically connects variouselectronic components to achieve a desired functionality. Some circuitboards use multiple layers to connect components and route signals.Components on a circuit board can range from simple electricalcomponents (e.g. resistors, capacitors, etc.), to more complexcomponents (e.g. ICs, system-on-chip (SoC), etc.). Among other things, aSoC is an integrated circuit that includes multiple components whichwork together to perform the functionality of a system. Various taskswithin the system can be partitioned into smaller tasks, each of whichmay be performed a respective sub-component of the SoC. Thesesub-components communicate with one another to achieve the overallsystem functionality. Here, modem 106 includes two complex components:Radio Frequency (RF) circuitry 108 and baseband circuitry 110. Forsimplicity's sake, the discussion of modem 106 will be reserved to thesecomponents. However, modem 106 can include additional or alternatecomponents, hardware, software and/or firmware without departing fromthe scope of the claimed subject matter. In some aspects, RF circuitry108 and/or baseband circuitry can be implemented as an IC and/or SoC.

RF circuitry 108 sends and receives wireless signals and/or data over awireless communication link via one or more antenna, while basebandcircuitry 110 performs real-time baseband processing of the wirelesssignals and/or data. To actualize wireless communication capabilities ofmodem 106, RF circuitry 108 and baseband circuitry 110 interconnect withone another to exchange data. As further described above and below,these interconnections can be susceptible to real-world influences thatcorrupt data as it is being transferred. In order to ensure robusthandling of corrupted data, RF circuitry 108 includes error-generator(s)112 and error-handler(s) 114. Similarly, baseband circuitry 110 includeserror-generator(s) 116 and error-handler(s) 118. While FIG. 1illustrates RF circuitry 108 and baseband circuitry 110 as each onlyincluding one error-generator and one error-handler, it is to beappreciated that this is merely for discussion purposes. That is, anysuitable number of error-generator components and/or error-handlercomponents can be included on RF circuitry 108 and baseband circuitry110 without departing from the scope of the claimed subject matter.

Error-generator(s) 112 and error-generator(s) 116 represent on-chiphardware error-generator components that introduce a data error patternonto a data line connecting at least two sub-components, as furtherdescribed below. Among other things, error-generator components overridedata transmissions coming in from a first (originating) sub-component ona respective data path, and output a specified data error pattern on thedata path into a second (recipient) sub-component. Dynamicconfigurations and/or alterations to an error-generator component cancontrol the timing of when a data error pattern is placed onto a dataline and/or the content of the data error pattern.

Error-handler(s) 114 and error-handler(s) 118 represent on-chiperror-hander components that receive input data, and perform a knownresponse to the received data. For example, an error-handler componentcan be “downstream” of a data line that is coupled to an error-generatorcomponent, where the error-handler component receives either direct datainput generated by the error-generator component or indirect data inputgenerated by the error-generator component. When the received dataincludes an error, an error-handler component recognizes the “corrupteddata”, and handles it in such a manner that prevents the correspondingsystem from hanging and/or halting (e.g. the corresponding system canrecover from the corrupted data).

Having described example operating environments in which various aspectscan be utilized, consider now a discussion of self-error injection inpoint-to-point connections in accordance with one or more aspects.

Self-Error Injection in Point-to-Point Connections

The complexity of a device sometimes translates into an increase in thenumber of hardware and/or software components contained within thedevice. At times, various functions performed by the device can bepartitioned and executed by respective components. In turn, thecomponents communicate with one another to request functionality, returnresults, indicate when an event has occurred, and so forth, to realizean overall objective. In hardware, communications can occur over datalines by transmitting electronic signal(s) with various waveforms and/orpatterns to represent information or data.

To further illustrate, consider FIG. 2, which includes examples 200 aand 200 b. Example 200 a illustrates a component 202 and a component 204communicating with one another via electronic signal 206 over data line208. Here, electronic signal 206 represents an ideal electronic signalflowing on data line 208 between the respective components. Since theelectronic signal is ideal, it is received by component 204 exactly assent by component 202. Any suitable type of electronic signal can besent between the components to represent any suitable type ofinformation. For simplicity's sake, data line 208 between component 202and component 204 is illustrated as a single data line connection with asingle electronic signal flowing between the two. However, data line 208can include multiple data line connections, each with a respectiveelectronic signal, without departing from the scope of the claimedsubject matter. In a digital link, electronic signals are transmitted toconvey digital information. Upon receiving electronic signal 206,component 204 extracts the information in a manner as agreed uponbetween the components, such as by comparing the voltage of electronicsignal 206 to a threshold value at instantaneous points in time todiscern if the corresponding data bit is a “0” or a “1”. This simpleexample is for discussion purposes only. As such, other suitable typesof electronic signals and/or information extraction processes can beused without departing from the scope of the claimed subject matter.When an electronic signal is sent cleanly, such as the ideal signal flowof electronic signal 206, component 204 receives all of the datatransmitted by component 202 without errors. In a real worldenvironment, however, various factors can distort a signal and, in turn,corrupt the data that is being sent.

Example 200 b illustrates component 202 and component 204 communicatingover data line 208 via electronic signal 210, where electronic signal210 includes distortions based upon physical factors. Here, physicalfactors, such as electromagnetic interference (EMI), noise, imperfectdata line materials, temperature fluctuations, etc., can modify physicalproperties of the signal, such as a resultant voltage. In turn, whencomponent 204 makes a decision as to whether the information is a “0” ora “1”, the alterations made to the ideal signal can yield incorrect data(e.g., a transmitted “1” is interpreted as a “0”). Thus, even though afirst component sends the correct information, the second component maynot receive the information properly due to distortion.

An on-chip, hardware error-generator component can be used to simulatevarious error conditions, such as those associated with corrupted data,between sub-components of a system. In turn, the data error simulationscan be used to test error handling functionality of the receivingsub-components. Having precise control of what error conditions aresimulated, and when they are simulated, ensures a more robust product byexercising the respective error handling functionality.

Continuing on with the above example of a wireless modem, now considerFIGS. 3a and 3b . FIGS. 3a and 3b include more detailed exampleimplementations of RF circuitry 108 and baseband circuitry 110 of FIG.1, respectively. As in the above case, the discussion of these exampleswill be reserved to the illustrated components. It is to be appreciatedthat other aspects can incorporate additional or lessfunctionality/circuitry without departing from the scope of the claimedsubject matter.

In this example, RF circuitry 108 is implemented as a SoC. Thesub-components of RF circuitry 108 include: analog-to-digital converter(ADC) 302, digital-to-analog converter (DAC) 304, link layersub-component 306, physical (PHY) layer sub-component 308, and SERDESsub-component 310. Generally speaking, ADC 302 receives an incoming RFsignal from a respective antenna, and generates digital samples from thesignal. DAC 304 receives digital samples, converts the samples to ananalog signal, and transmits the analog signal out a respective antenna.Link layer sub-component 306 contains logic that is used to interconnectRF circuitry 108 to other components using communication protocols,while PHY layer sub-component 308 represents functionality thatconfigures hardware to generate data signals associated with thecommunication protocol(s) managed by link layer sub-component 306.SERDES sub-component 310 represents an ability to send and receive dataoff-chip. Among other things, SERDES sub-component 310 includes logicthat converts data transmissions between serial and parallel formats.

To help maintain the interconnections between RF circuitry 108 andexternal or internal components, link layer sub-component 306 sends datato PHY layer sub-component 308 using data line 312. Similarly, PHY layersub-component 308 sends data to SERDES sub-component 310 using data line314. Data line 312 and data line 314 can be digital links used totransfer digital information between the different components. Asdiscussed above, the electronic signals used to transfer the informationover data line 312 and data line 314 are subject to modification due tophysical factors. Consequently, there is a potential that componentsdownstream from link layer sub-component 306 or PHY layer sub-component308 may receive corrupted data. By inserting error-handler componentsinto the system, the downstream components can respond to the corrupteddata without jeopardizing operation of the overall system. However, itis helpful to further test the error handling to ensure that it isworking properly. Some aspects insert data error patterns onto thesedata paths using on-chip hardware error-generator components as a way togenerate each potential data corruption scenario on command.

RF circuitry 108 includes error-generator component 316, which iscoupled to data path 312 via an error insertion circuit in the form of ahardware multiplexer (MUX) 318, and error-generator component 320, whichis coupled to data path 314 via error insertion circuit in the form of aMUX 322. While the error insertion circuits are each illustrated here asa MUX, it is to be appreciated that other types of circuits, controllogic components, gates, and/or hardware can be utilized withoutdeparting from the scope of the claimed subject matter (i.e., anarithmetic logic unit (ALU), an eXclusive OR (XOR) gate, AND gates, ORgates, inverter (NOT) gates, etc.). The coupling of an error-generatorcomponent to a data line via insertion circuitry and/or control logicyields configurable hardware components that can override datatransmissions on a respective data path, and additionally allow datatransmissions to travel along their respective data path unaltered. Interms of this example, data transmitted on data path 312 can passthrough MUX 318 without modification when error-generator component 316is disabled, or can be altered with a data error pattern whenerror-generator component 316 is enabled. Similarly, data transmitted ondata path 314 can pass through MUX 322 without modification, or can bealtered with a data error pattern generated by error-generator component320. Thus, data transmissions can be modified according to a variety ofselected data error patterns, and in a variety of manners, as furtherdescribed below. Further, data modifications generated by anerror-generator component can replace a portion of the originaltransmitted data, can be interspersed with the original transmitteddata, or can replace all of the original transmitted data. The resultantdata is then transmitted “downstream” for further processing. Here, thecumulative effect of either one or both of error-generator component 316and error-generator component 320 is sent out through SERDESsub-component 310 to a recipient, such as baseband circuitry 110. It isto be appreciated that, when multiple error-generator components resideon a same chip, the error-generator components can be enabled at a sametime, or independent of one another.

FIG. 3b . illustrates an example implementation of baseband circuitry110 that connects into RF circuitry 108 of FIG. 3a . As in the case ofRF circuitry 108, baseband circuitry 110 is illustrated as a SoC withsimilar sub-components (e.g., SERDES sub-component 324, PHY layersub-component 326 and link layer sub-component 328). Incoming (off-chip)data is received through SERDES sub-component 324, and forwarded to PHYlayer sub-component 326 over data line 330. Among other things, the datareceived over data line 330 is passed to error-handler component 332 forprocessing. Error-handler component 332 represents on-chip errorhandling functionality that resides in PHY layer sub-component 326 andis configured to process incoming data in a context pertains to PHYlayer functionality (e.g., recognizes and/or processes data in a formatassociated with PHY layer functionality). Similarly, link layer ofsub-component 328 receives data over data line 334, which is thenprocessed by on-chip error-handler component 336. Both the error-handlercomponent 332 and error-handler component 336 can be considered“downstream” from error-generator component 316 and error-generatorcomponent 320 since each error handler component (indirectly) receivesdata generated by, or based upon, the error-generator components. Thus,the error handling functionality of baseband circuitry 110 can be testedby inserting data error patterns “upstream”.

In this example, each error-handler component of baseband circuitry 110is an intended recipient of one or more data error simulations generatedby any combination of error-generator component 316 and/orerror-generator component 320. As in the cases of the error-generatorcomponents, the error-handler components can be placed in any suitablelocation and/or on any suitable sub-component of baseband circuitry 110.By cycling through various data error simulation scenarios, the on-chiperror-hander components of baseband circuitry 110 can be tested toensure a robust product. It is to be appreciated that, while the abovediscussion uses the context of error-generator components placed on-chipon RF circuitry 108 for testing purposes of error-handler components onbaseband circuitry 110, the various techniques described are applicableto other aspects. For example, in some cases, baseband circuitry 110includes one or more on-chip error-generator components throughout anoutgoing data path towards RF circuitry 108. Similarly, RF circuitry 108can include one or more error handler components on its respectivesub-components.

By inserting a hardware error-generator component along a data path,testing routines are able to more precisely control which errorconditions occur and when the error conditions occur. In some cases, thedata patterns generated by a hardware error-generator component can betailored to the type of data being transmitted via the data path onwhich the patterns are inserted. Consider error-generator component 316,which is inserted between link layer sub-component 306 and PHY layersub-component 308. In some aspects, link layer sub-component 306 and PHYlayer sub-component 308 communicate with one another using structureddata packets. Among other things, structured data packets have apre-agreed upon data partitioning between the communicating parties. Forexample, some data packets begin with a preamble or training sequence,include a synchronization word, a checksum for error checking, a datapacket header, message type fields, identification fields, payload data,a cyclic redundancy check (CRC) field, and so forth. Based on thepre-agreed upon structure, the transmitting and receiving entitiesinterpret certain groupings of data to have different meanings.Accordingly, in some aspects, error-generator component 316 tracks thephase of a data packet as it is being transmitted (e.g., keeps track ofwhich phase and/or field of a structured data packet is currently beingtransmitted over a data line) and inserts data error simulation in aparticular location within the data packet. Any suitable field can betracked and/or modified, such as a data packet header modification, aCRC field error, payload data errors, a forced error bit on a data lane,and so forth. In some cases, an error-generator component includes astate machine to track the phase of a data packet as it is beingtransmitted to identify the current fields.

While data error simulations can be based upon altering specific fieldsof a structured data packet, they can also be timing-based. Forinstance, instead of tracking the phase of the data that is beingtransferred between components, it may be desirable to instead inserterrors at periodic time intervals, over specified interval windows,and/or random intervals. These intervals can be based upon any suitabletime and/or unit of measure, such as a clock count, a bit count, aspecified window of time, and so forth. When an identified intervaloccurs, the error-generator component inserts data onto the data line tosimulate specified error conditions, such as a stuck-high bit, astuck-low bit, a random bit pattern, a random bit flip, a bit-shift, andso forth.

In addition to inserting data error simulations at random points intime, some aspects insert random errors. For instance, when modifying achecksum value of a data packet as further discussed above, the dataerror simulation can be based upon the currently transmitted checksumvalue. However, in other aspects, the data can simply be randomlyaltered, such as through random bit-flipping, either at specific pointsin time, or at random points in time, specified error conditions atspecified points in time, or any combination thereof Thus, anerror-generator can be configured to simulate phase (e.g. data field)level errors, timing level errors, random errors, or any combinationthereof

By having precise control of data error simulation on a data line, aproduct can be tested more thoroughly for a number of scenarios,including corner case scenarios. The precise generation of an errorallows an observer to verify whether the error is handled properly bythe receiving component. Further, the on-chip nature of theerror-generator components, as well as the error-handler componentsdiscussed above, allow for verification of behavior during simulationand emulation of a silicon chip design during thepre-silicon/prefabrication process. For example, an on-chipconfiguration register can be used throughout the various developmentphases to configure an error-generator component.

On-chip configuration registers of ICs and/or SoCs can be used tocontrol the behavior of various on-chip components, such an on-chiphardware error-generator component. For instance, different input valuesto a configuration register can alter how and/or when theerror-generator component inserts data error simulations on to acorresponding data path. This can be achieved in any suitable manner,such as by enabling or disabling a data error simulation state machinein the error-generator component that monitors a phase of data beingtransmitted effective to identify various data fields. The data inputcan also be used to configure the timing of when data errors aresimulated, whether the data is random in nature, etc. Thus, differentconfigurations of an error-generator component correspond to differentdata being written into a configuration register. There can be a 1-to-1correspondence between an error-generator component and a configurationregister (where each on-chip error-generator component has a respectiveconfiguration register), or there can be a 1-to-many correspondence(where a master configuration register is used to configure multipleerror-generator components, or multiple configuration registers are usedto configure one error-generator component). Regardless, the behavior ofan error-generator component can be modified, enabled, or disabled bywriting the corresponding configuration data or commands into the properregister. The on-chip nature of these configuration registers give adeveloper uniform access to an error-generator component, regardless ofwhere in development the error-generator component is being accessed.

One advantage of on-chip error-generator components is the ability toprecisely test various error scenarios, and corresponding error handlingtechniques, throughout various phases of the development cycle usingexisting development tools. In some cases, the same test sequences canbe used. The on-chip nature of the error-generator components, as wellas the error-handler components discussed above, allow for verificationof behavior during simulation and emulation of a silicon chip designduring the pre-silicon/prefabrication process. For example, in thepre-fabrication development stage of an IC, the error-generatorcomponent configuration registers can be accessed and/or set using testscripts run in conjunction with emulation software that simulates the ICand/or various components of the IC (e.g., emulation of an on-chiphardware error-generator, emulation of one or more sub-components of theIC, emulation of error-handler components of the IC, etc.). This allowsfor pre-fabrication testing of not only the on-chip hardwareerror-generator components of an emulated IC, but the correspondingerror-handler components as well. These same testing routines can alsobe utilized post-fabrication to assess the hardware aspects of theconfiguration registers and/or the error-generator components, as wellas when the IC is included into a design or product. Thus, a multitudeof platforms can use at least some of the same testing procedures thatemploy on-chip error-generator components.

FIG. 4 illustrates an example method in accordance with one or moreaspects. This method can be performed by hardware, firmware, software,or any suitable combination thereof In some aspects, the method can beimplemented in hardware via one or more sub-components on asystem-on-chip, as further described below above and below.

At block 402, an error-generator component receives an error simulationinput. The error simulation input can be received in any suitable mannerFor example, in some cases, the error simulation input is received via aregister write to a configuration register associated with theerror-generator component. At times, the error-generator component is asub-component of an IC. The error simulation input can be any suitabletype of input, such as data over one or more data lines, data bitsstored at one or more addresses in computer-readable memory hardware,and so forth. Alternately or additionally, the error-generator componentcan receive an event, such as hardware or software interrupt, indicatingthat data error simulation input is available.

At block 404, responsive to receiving the error simulation input, theerror-generator component determines a data error pattern. At times, thedata error pattern is a modification to binary “0” or “1” bits, such asa random flip of a bit. Another example of a data error pattern is amodification to particular field in a data packet. Any suitable type ofdata error pattern can be determined, such as a data pattern simulatinga stuck-high bit, a data pattern simulating a stuck-low bit, a datapattern simulating a random-bit flip, a data pattern simulating a forcederror bit on the data line, a data pattern simulating a CRC field error,a data pattern simulating a data packet header error, a data patternsimulating a training sequence data error, and so forth.

Alternately or additionally, the error-generator component can determinetiming insertion information from the error simulation input, such as:an indication to periodically insert a data error pattern on the dataline, an indication to randomly insert a data error pattern on the dataline, an indication of a count metric for a number data error patternsto insert, an indication of a timing window in which to insert dataerror patterns, and so forth. In some cases, the selection of a dataerror pattern is performed by one or more logic gates in hardware.

At block 406, responsive to selecting a data error pattern, theerror-generator inserts the data error pattern on a data path. Forexample, as described above and below, the error-generator component canbe coupled to one or more error insertion circuit that manages a digitaldata line. When the error insertion circuit and the error-generatorcomponent are enabled, an electronic signal traveling on a digital dataline can be modified to simulate the selected data error pattern. Insome aspects, a hardware error-generator component tracks a phase of astructured data packet being transmitted on a data line, and inserts thedata error pattern in at least one field of the structured data packet,such as a training field that is used by a receiver to detect a packetor tune to a signal, a data packet header, etc. Inserting the data errorpattern can be based on timing data, such as a clock count at random orperiodic intervals. The data error pattern can be interspersed with dataoriginating from a first sub-component to a second sub-component via adigital data line, such as by replacing a portion of the dataoriginating from the first sub-component on the digital data line, orcan replace all of the data originating from the first sub-component onthe digital data line.

Thus, on-chip, hardware error-generator components provide a low costtesting solution with controllable outcomes since the error-generatorcomponents are fabricated in a same manner as the functionality beingtesting. The predictable control of simulating data errors allows forthorough testing of error handling functionality in multiple platformswithout a need for additional hardware or testing equipment. Havingdescribed various embodiments of on-chip, hardware error-generatorcomponents, consider now an example system that can be utilized toimplement one or more of the above-described embodiments.

Example System and Device

FIG. 5 illustrates an example system-on-chip (SoC) 500, which includescomponents capable of implementing aspects of self-error injection viahardware error-generator components. In some aspects, system-on-a-chip500 is an IC comprising a set of electronic circuits on one or moresubstrate of semiconductor material, such as silicon, germanium, galliumarsenide, and so forth. Further, system-on-chip 500 may be implementedin, or as, any suitable electronic device, such as a modem, broadbandrouter, access point, cellular phone, smart-phone, gaming device, laptopcomputer, net book, smart-phone, network-attached storage (NAS) device,or any other device that may implement self error-injection.System-on-chip 500 can be configured to perform any suitable type offunctionality. For example, in some aspects, system-on-chip 500implements an RF signal processing system, such as RF circuitry 108 ofFIG. 1. Alternately or additionally, system-on-chip 500 implements abaseband signal processing system functionality, such as that providedby baseband circuitry 110 of FIG. 1.

System-on-chip 500 includes sub-component 502 and sub-component 504.These sub-components are used to generally represent partitionedfunctionality contained within system-on-chip 500. In some cases, thesub-components are partitioned circuits that included varyingcombinations of transistors, logic gates, flip flops, MUX-es,computer-readable memory storage, and so forth, to perform theirrespective partitioned functionality. At times, the sub-components areconfigured to include circuitry capable of processing analog and/ordigital signals. For example, in some aspects, sub-component 502performs link layer functionality, such as that performed by link layersub-component 306 of FIGS. 3a and 3b . Alternately or additionally,sub-component 504 performs PHY layer functionality, such as thatperformed by PHY layer 308 of FIGS. 3a and 3 b.

System-on-chip 500 also includes error-generator component 506, errorinsertion component 508, and configuration register 510, which can beused together to inject one or more data error simulations on the datalines coupling sub-component 502 and sub-component 504. In some aspects,the functionality of error-generator component 506 and/or errorinsertion component 508 can be controlled by writing data intoconfiguration register 510. For example, error-generator component 506and/or error insertion component 508 can receive configuration datathrough preassigned addresses accessible through configuration register510. In some embodiments, the data input to configuration register 510enables or disables a data error simulation state machine inerror-generator component 506 that monitors a phase and/or a state ofdata being modified, and/or configure the timing of when data errors aresimulated, as further described above. For simplicity's sake,system-on-chip 500 is illustrated as containing one error-generatorcomponent, one coupling logic component, and one configuration register.However, system-on-chip 500 can include any suitable combination innumber of these components and registers without departing from thescope of the claimed subject matter.

Data line 512 represents a digital data line that can be used bysub-component 502 to transmit data and/or information, via an electronicsignal, to sub-component 504. Here, data line 512 is an input to errorinsertion component 508, while data line 514 is an output digital dataline from the error insertion component 508. When error-generatorcomponent 506 is disabled (e.g., not generating data error simulations),the data transmitting on data line 512 passes through error insertioncomponent 508 to sub-component 504 by way of data line 514. Whenerror-generator component 506 is enabled (e.g., simulating data errors),error insertion component 508 injects the simulated errors onto dataline 514. In some embodiments, all of the data transmitted on data line512 is replaced (such as a whole data packet), while in otherembodiments, data errors are interspersed with the data transmitted ondata line 514 at various locations and/or point in time. Thus, errorinsertion component 508 contains circuitry and/or logic that couplesdata line 512 with error-generator component 506 to output resultantdata signals over data line 514. Error insertion component 508 can beimplemented in any suitable manner, such as through the use of a MUX, anXOR logic gate, and so forth.

Various techniques may be described herein in the general context ofhardware components, software components, firmware components, or anycombination thereof Generally, hardware components can includeinterconnected electronic components that perform analog and/or digitaloperations based upon input electronic signals and/or power. Theinterconnected electronic components can range widely, such as, forexample, discrete components (e.g., resisters, capacitors, transistors,etc.), integrated circuits (ICs), semiconductor based components,optically based components, central processing units (CPUs),Input/Output (I/O) ports, computer-readable memory devices, or anycombination thereof. Alternately or additionally, the electroniccomponents can be any combination of passive or active electroniccomponents. These examples are merely for discussion purposes, and arenot intended to limit the scope of the claimed subject matter.

Generally, software components includes routines, programs, objects,data structures, and so forth that perform particular tasks or implementparticular abstract data types. The tasks performed by the softwarecomponents can range from low-level hardware access, such asprocessor-executable instructions that perform register reads andwrites, to operating system components that manage access to computerhardware and provide common services and/or programs, to applicationcomponents that utilize services provided by an operating system tointeract with a user. These various components and techniques may bestored on or transmitted across some form of computer readable media,and are, at times, executable by one or more processors.

“Computer-readable storage media” and/or computer-readable memorydevices include volatile and non-volatile, removable and non-removablemedia implemented in any method or technology for storage ofinformation. Further, the contents contained within the media and/ormemory devices can be accessed by a computer or processor. Storage mediaand/or memory devices can be implemented by any suitable type of device,such as, by way of example, and not of limitation, RAM, ROM, EEPROM,flash memory or other memory technology, CD-ROM, digital versatile disks(DVD) or other optical storage, magnetic cassettes, magnetic tape,magnetic disk storage or other magnetic storage devices, or any othermedium which can be used to store the desired information. Theinformation can include any suitable type of data, such as computerreadable instructions, sampled signal values, data structures, programcomponents, or other data. These examples, and any combination ofstorage media and/or memory devices, are intended to fit within thescope of non-transitory computer-readable media.

Firmware components include electronic components with programmablememory configured to store executable instructions that direct theelectronic component how to operate. In some cases, the executableinstructions stored on the electronic component are permanent, while inother cases, the executable instructions can be updated and/or altered.At times, firmware components can be used in combination with hardwarecomponents and/or software components.

The term “component”, “module”, and “system” are intended to refer toone or more computer related entities, such as hardware, firmware,software, or any combination thereof, as further described above. One ormore components. At times, a component may refer to a process and/orthread of execution that is defined by processor-executableinstructions. Alternately or additionally, a component may refer tovarious electronic and/or hardware entities.

CONCLUSION

Various aspects describe an on-chip, hardware error-generator component.In some cases, the hardware error-generator component connects to a datapath between two components contained within a same chip. Upon receivingan error simulation input, the hardware error-generator componentmodifies data being transmitted on the data path by inserting a datapattern that simulates an error condition. Alternately or additionally,the hardware error-generator randomly alters one or more of thetransmitted data bits.

Although the aspects have been described in language specific tostructural features and/or methodological acts, various aspects definedin the appended claims are not necessarily limited to the specificfeatures or acts described. Rather, the specific features and acts aredisclosed as example forms of implementing the various aspects.

What is claimed is:
 1. A device for testing error handling, the devicecomprising: at least one error insertion circuit; an on-chip hardwareerror-generator component coupled, via the at least one error insertioncircuit, to at least one data line between two sub-components in thedevice, the on-chip hardware error-generator component configured to:receive an error simulation input; determine a data error pattern based,at least in part, on the error simulation input; and insert the dataerror pattern, via the at least one error insertion circuit, on the atleast one data line effective to generate an error condition.
 2. Thedevice of claim 1, wherein the data error pattern comprises a data errorpattern associated with at least one of: a stuck-high bit; a stuck-lowbit; a random bit flip; or a forced error bit on the data line.
 3. Thedevice of claim 1 further comprising at least one configuration registerassociated with the on-chip hardware error-generator component andconfigured to control the data error pattern inserted by the on-chiphardware error-generator on the at least one data line.
 4. The device ofclaim 1, wherein the on-chip hardware error-generator component isconfigured to modify a data packet header of a data packet transmittedon the at least one data line.
 5. The device of claim 1, wherein theon-chip hardware error-generator component is further configured torandomly insert the data error pattern on the at least one data line. 6.The device of claim 1, wherein the on-chip hardware error-generatorcomponent is a sub-component of an integrated circuit (IC).
 7. Thedevice of claim 1, wherein the at least one error insertion circuitcomprises a hardware multiplexer (MUX).
 8. A method for testing errorhandling, the method comprising: receiving, using a hardwareerror-generator component, an error simulation input; determining, usingthe hardware error-generator component, a data error pattern to inserton at least one digital data line coupled to the hardwareerror-generator component; and inserting, using the hardwareerror-generator component, the data error pattern on the at least onedigital data line effective to generate an error condition.
 9. Themethod of claim 8, wherein inserting the data error pattern on the atleast one digital data line is based, at least in part, on a clockcount.
 10. The method of claim 8 further comprising tracking a phase ofa structured data packet being transmitting on the at least one digitaldata line effective to identify each data field of the structured datapacket as it is being transmitted on the at least one digital data line;and inserting the data error pattern in at least one field of thestructured data packet based, at least in part, on the tracked phase.11. The method of claim 10, wherein the at least one field comprises atraining field.
 12. The method of claim 8, wherein inserting the dataerror pattern comprises inserting a data error pattern associated withcommunications between a physical (PHY) layer sub-component and aSERializer/DESerializer (SERDES) sub-component.
 13. The method of claim8, wherein inserting the data error pattern on the at least one dataline further comprises inserting the data error pattern on the at leastone data line at periodic time intervals.
 14. The method of claim 8,wherein inserting the data error pattern on the at least one digitaldata line further comprises interspersing the data error pattern withoriginal data transmitted on the at least one digital data line.
 15. Anapparatus for testing error handling, the apparatus comprising: anon-chip sub-component of the apparatus operatively coupled to a datapath; and an on-chip hardware error-generator component operativelycoupled to the data path and comprising: means for receiving errorsimulation input; means for determining at least one data error patternbased, at least in part, on the error simulation input; and means forinserting the at least one data error pattern on the data path effectiveto generate an error condition into the on-chip sub-component of theapparatus.
 16. The apparatus of claim 15, wherein the means forinserting the at least one data error pattern on the data path furthercomprises means for interspersing the data error pattern with dataoriginating from a second on-chip sub-component of the apparatus. 17.The apparatus of claim 15, wherein the means for determining the atleast one data error pattern further comprises means for determiningtiming insertion information associated with when to insert the at leastone data error pattern on the data path.
 18. The apparatus of claim 15,wherein the on-chip sub-component comprises a physical (PHY) layersub-component associated with a communication protocol.
 19. Theapparatus of claim 15, wherein the apparatus comprises a radio frequency(RF) integrated circuit (IC) associated with a wireless modem.
 20. Theapparatus of claim 15, wherein the at least one data error patterncomprises a data error pattern associated with at least one of: astuck-high bit; a stuck-low bit; a random bit flip; a forced error biton the data path; a cyclic redundancy check (CRC) field error; a datapacket header error; or a training sequence data error.
 21. Theapparatus of claim 15, wherein the means for receiving error simulationinput further comprises at least one configuration register associatedwith the means for generating the at least one data error pattern. 22.The apparatus of claim 15, wherein the means for inserting the at leastone data error pattern on the data path comprises at least one of: amultiplexer (MUX); or an eXclusive OR (XOR) gate.
 23. One or morecomputer-readable memory devices comprising processor-executableinstructions which, responsive to execution by at least one processor,perform operations to simulate on-chip error generation using one ormore components of an emulated integrated circuit (IC), the operationscomprising: receiving an error simulation input at an on-chip hardwareerror-generator component of the emulated IC; determining a data errorpattern based, at least in part, on the error simulation input; andinserting the data error pattern on at least one data line coupled tothe on-chip hardware error-generator effective to generate an errorcondition into a sub-component of the emulated IC that is coupled to theat least one data line.
 24. The one or more computer-readable memorydevices of claim 23, wherein determining the data error patterncomprises determining a data error pattern associated with at least oneof: a stuck-high bit; a stuck-low bit; a random bit flip; or a forcederror bit on the data line.
 25. The one or more computer-readable memorydevices of claim 23, wherein receiving the error simulation inputcomprises receiving the error simulation input via a configurationregister associated with the on-chip hardware error-generator componentof the emulated IC.
 26. The one or more computer-readable memory devicesof claim 23, wherein inserting the data error pattern on the at leastone data line coupled to the on-chip hardware error-generator comprisesmodifying a data packet header of a data packet transmitted on the atleast one data line to the sub-component of the emulated IC.
 27. The oneor more computer-readable memory devices of claim 26, wherein theoperations to simulate on-chip error generation using one or morecomponents of an emulated IC comprise using one or more components of anemulated baseband circuit IC.
 28. The one or more computer-readablememory devices of claim 23, wherein inserting the data error pattern onthe at least one data line comprises inserting the data pattern on theat least one data line at periodic time intervals.
 29. The one or morecomputer-readable memory devices of claim 23 further configured toperform operations comprising: receiving data input at an error-handlercomponent of the emulated IC; identifying at least some corrupted datain the data input using the error-handler component; and responding tothe at least some corrupted data using the error-handler componenteffective to prevent the emulated IC from halting operation.
 30. The oneor more computer-readable memory devices of claim 23, wherein insertingthe data error pattern on the at least one data line comprises trackinga phase of a data packet being transmitted over the at least one dataline effective to determine when to insert the data error pattern on theat least one data line.